Conventionally, the data driving apparatus used in a large-scaled display is realized by at least two data driving circuits coupled in parallel; and, to have the benefits of one single integration chip, these data driving circuits as well as their associated timing controllers are integrated into one single chip.
However, when these data driving apparatuses receive and process the data of a to-be-displayed image frame according to a specific transmission protocol (e.g., transmission protocol of the Mobile Industry Processor Interface, MIPI) for saving power by stopping the transmission of data, the at least two timing controllers may operate according to the clocks generated by the respective clock generators. Because these individual clock generators may not generate clocks with the same frequency, the data driving circuits in the conventional data driving apparatus may not be able to output data synchronously.